Clock and Reset

All 65xx systems require external clock and reset signals to operate, the fennec generates theirs through a 'Clock and Reset Circuit built around two 74-series logic chips. Of note is this circuit's use of a dynamically stretched clock to allow the system to run at one of two speeds, a standard base speed and faster turbo speed, with the later being optionally enabled by peripherals. The following signals are generated by the clock and reset module and are available for general use:


 * ø2 - The main system clock used by the CPU, variable period according to state of the  line
 * ø1 - Inverted ø2
 * øT - "Turbo" clock, a constant clock always running at the max turbo rate, available for any peripherals that require a constant clock speed.
 * /RST - Reset signal, inverted
 * RST - Reset signal, non-inverted

Note: The timings of these signals has not yet been finalized and will be subject to change as development continues.

Clock
The clock signals are all derived from diving the same base oscillator,   is half of its rate, while the standard system speed will be some pre-determined divisor of. Specific values for these frequencies have not yet been settled on.

The clock signal  can easily have its speed modulated by a peripheral through the use of the   line, pulling this line low will seamlessly switch   to match , starting from the time   goes high. In the base system, RAM is wired to enable Turbo by default, meaning that has long as the system is executing from RAM it can be assumed to be running at its max speed.

Note: In the current setup special care must be taken by the peripheral to ensure that  is gated to only go low when  is high, in order for proper operation of the circuit. However its possible that future revisions of the hardware will perform this gating automatically.